VEC A VHDL Entity Converter
VEC parses your VHDL source for entity declaration and transforms this information into various output formats.
Output formats
Schematic symbols
Create beautiful symbols representing your entity. VEC is capable of generating the following formats
Text output
Generate a table of your entity's ports and generics. Tables can be generated in the following languages
Fully customizable
VEC gives you the ability to tune it to match your needs. You can adjust the visual appearance of generated schematic symbols, table formatting, etc.